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fn8165 rev.3.00 page 1 of 20 august 29, 2006 fn8165 rev.3.00 august 29, 2006 x9250 low noise/low power/spi bus/256 taps quad digitally controlled potentiometers (xdcp?) datasheet features ? four potentiometers in one package ? 256 resistor taps/pot - 0.4% resolution ? spi serial interface ? wiper resistance, 40 ? typical @ v cc = 5v ? four nonvolatile data r egisters for each pot ? nonvolatile storage of wiper position ? standby current < 5a max (total package) ? power supplies v cc = 2.7v to 5.5v v+ = 2.7v to 5.5v vC = -2.7v to -5.5v ? 100k ? , 50k ? total pot resistance ? high reliability endurance C 100,000 dat a changes per bit per register register data retention - 100 years ? 24 ld soic, 24 ld tssop ? dual supply version of x9251 ? pb-free plus anneal ava ilable (rohs compliant) description the x9250 integrates 4 digitally controlled potentiometers (xdcp) on a monolithic cmos integrated circuit. the digitally controlled potentiometer is implemented using 255 resistive elements in a series array. between each element are tap points connected to the wiper terminal through switches. the position of the wiper on the array is controlled by the user through the spi bus interface. each potentiometer has associated with it a volatile wiper co unter register (wcr) and 4 nonvolatile data registers (dr0:dr3) that can be directly written to and read by the user. the contents of the wcr controls the position of the wiper on the resistor array though the switches. power up recalls the contents of dr0 to the wcr. the xdcp can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. block diagram r 0 r 1 r 2 r 3 wiper counter register (wcr) resistor array v h1 /r h1 v l1 /r l1 r 0 r 1 r 2 r 3 wiper counter register (wcr) interface and control circuitry cs sck a0 a1 v h0 /r h0 v l0 /r l0 data 8 v w0 /r w0 v w1 /r w1 so si r 0 r 1 r 2 r 3 wiper counter register (wcr) resistor array pot 2 v h2 /r h2 v l2 /r l2 v w2 /r w2 r 0 r 1 r 2 r 3 wiper counter register (wcr) resistor array pot 3 v h3 /r h3 v l3 /r h3 v w3 /r w3 pot1 hold wp pot 0 v cc v ss v+ v-
x9250 fn8165 rev.3.00 page 2 of 20 august 29, 2006 ordering information part number part marking v cc limits (v) potentiometer organization (k ? ) temp. range (c) package pkg. dwg. # x9250ts24i x9250ts i 5 10% 100 -40 to +85 24 ld soic (300 mil) m24.3 x9250ts24iz (note) x9250ts zi -40 to +85 24 ld soic (300 mil) (pb-free) m24.3 x9250tv24i x9250tv i -40 to +85 24 ld tssop (4.4mm) mdp0044 x9250tv24iz (note) x9250tv zi -40 to +85 24 ld tssop (4.4mm) (pb-free) mdp0044 X9250US24 x9250us 50 0 to +70 24 ld soic (300 mil) m24.3 X9250US24z (note) x9250us z 0 to +70 24 ld soic (300 mil) (pb-free) m24.3 X9250US24i x9250us i -40 to +85 24 ld soic (300 mil) m24.3 X9250US24iz (note) x9250us zi -40 to +85 24 ld soic (300 mil) (pb-free) m24.3 x9250uv24i x9250uv i -40 to +85 24 ld tssop (4.4mm) mdp0044 x9250uv24iz (note) x9250uv zi -40 to +85 24 ld tssop (4.4mm) (pb-free) mdp0044 x9250ts24-2.7 x9250ts f -2.7 to 5.5 100 0 to +70 24 ld soic (300 mil ) m24.3 x9250ts24z-2.7 (note) x9250ts zf 0 to +70 24 ld soic (300 mil) (pb-free) m24.3 x9250ts24i-2.7* x9250ts g -40 to +85 24 ld soic (300 mil) m24.3 x9250ts24iz-2.7* (note) x9250ts zg -40 to +85 24 ld soic (300 mil) (pb-free) m24.3 x9250tv24i-2.7 x9250tv g -40 to +85 24 ld tssop (4.4mm) mdp0044 x9250tv24iz-2.7 (note) x9250tv zg -40 to +85 24 ld tssop (4.4mm) (pb-free) mdp0044 X9250US24-2.7* x9250us f 50 0 to +70 24 ld soic (300 mil) m24.3 X9250US24z-2.7* (note) x9250us zf 0 to +70 24 ld soic (300 mil) (pb-free) m24.3 X9250US24i-2.7 x9250us g -40 to +85 24 ld soic (300 mil) m24.3 X9250US24iz-2.7 (note) x9250us zg -40 to +85 24 ld soic (300 mil) (pb-free) m24.3 x9250uv24-2.7 x9250uv f 0 to +70 24 ld tssop (4.4mm) mdp0044 x9250uv24z-2.7 (note) x9250uv zf 0 to +70 24 ld tssop (4.4mm) (pb-free) mdp0044 x9250uv24i-2.7 x9250uv g -40 to +85 24 ld tssop (4.4mm) mdp0044 x9250uv24iz-2.7 (note) x9250uv zg -40 to +85 24 ld tssop (4.4mm) (pb-free) mdp0044 *add "t1" suffix for tape and reel. note: intersil pb-free plus anneal products employ special pb-fr ee material sets; molding compounds/die attach materials and 10 0% matte tin plate termination finish, which are rohs compliant and compatible wit h both snpb and pb-free solderi ng operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exc eed the pb-free requirements of ipc/jedec j std-020.
x9250 fn8165 rev.3.00 page 3 of 20 august 29, 2006 pin descriptions serial output (so) so is a serial data output pi n. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock. serial input si is the serial data input pin. all opcodes, byte addresses and data to be written to the pots and pot registers are input on this pin. data is latched by the rising edge of the serial clock. serial clock (sck) the sck input is used to clock data into and out of the x9250. chip select (cs ) when cs is high, the x9250 is deselected and the so pin is at high impedance, and (unless an internal write cycle is underway) the de vice will be in the standby state. cs low enables the x9250, placing it in the active power mode. it should be noted that after a power-up, a high to low transition on cs is required prior to the start of any operation. hold (hold ) hold is used in conjunction with the cs pin to select the device. once the part is selected and a serial sequence is underway, hold may be used to pause the serial communication with the controller without resetting the serial sequence. to pause, hold must be brought low while sck is low. to resume communication, hold is brought high, again while sck is low. if the pause feature is not used, hold should be held high at all times. device address (a 0 - a 1 ) the address inputs are used to set the least significant 2 bits of the 8-bit slave add ress. a match in the slave address serial data stream must be made with the address input in order to in itiate communication with the x9250. a maximum of 4 devices may occupy the spi serial bus. potentiometer pins v h /r h (v h0 /r h0 - v h3 /r h3 ), v l /r l (v l0 /r l0 - v l3 /r l3 ) the r h and r l pins are equivalent to the terminal connections on a mechanical potentiometer. v w /r w (v w0 /r w0 - v w3 /r w3 ) the wiper pins are equivalent to the wiper terminal of a mechanical potentiometer. hardware write protect input (wp ) the wp pin when low prevents nonvolatile writes to the data registers. analog supplies (v+, v-) the analog supplies v+, v- are the supply voltages for the xdcp analog section. pin configuration pin names symbol description sck serial clock si, so serial data a 0 -a 1 device address v h0 /r h0? v h3 /r h3 , v l0 /r l0? v l3 /r l3 potentiometer pins (terminal equivalent) v w0 /r w0? v w3 /r w3 potentiometer pins (wiper equivalent) wp hardware write protection v+,v- analog supplies v cc system supply voltage v ss system ground nc no connection s0 a0 v w3 /r w3 v+ v cc v l0 /r l0 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 hold sck v l2 /r l2 v h2 /r l2 v w2 /r w2 v? v ss v w1 /r w1 v h1 /r h1 v l1 /r l1 soic/tssop x9250 v h3 /r h3 14 13 11 12 v l3 /r l3 v h0 /r h0 v w0 /r w0 cs a1 si wp
x9250 fn8165 rev.3.00 page 4 of 20 august 29, 2006 device description serial interface the x9250 supports the spi interface hardware conventions. the device is accessed via the si input with data clocked in on the rising sck. cs must be low and the hold and wp pins must be high during the entire operation. the so and si pins can be connected together, since they have three state outputs. this can help to reduce system pin count. array description the x9250 is comprised of four resistor arrays. each array contains 255 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (v h /r h and v l /r l inputs). at both ends of each array and between each resistor segment is a cmos switch connected to the wiper (v w /r w ) output. within each individual array only one switch may be turned on at a time. these switches are cont rolled by a wiper counter register (wcr). the 8 bits of the wcr are decoded to select, and enable, one of 256 switches. wiper counter register (wcr) the x9250 contains four wiper counter registers, one for each xdcp pote ntiometer. the wcr is equivalent to a serial-in, parallel-out regi ster/counter with its outputs decoded to select one of 25 6 switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written directly by the host via the write wiper counter register instru ction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the xfr data register or global xfr data register instructions (parallel load); it can be mo dified one step at a time by the increment/decrement instru ction. finally, it is loaded with the contents of its data register zero (dr0) upon power-up. the wiper counter register is a volatile register; that is, its contents are lost when the x9250 is powered-down. although the register is aut omatically loaded with the value in r0 upon power-up, this may be different from the value present at power-down. data registers each potentiometer has four 8-bit nonvolatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the associated wiper counter register. all operations changing data in one of the data registers is a nonvolatile operation and will take a maximum of 10ms. if the application does not require storage of multiple settings for the potentiometer, the data registers can be used as regular memory locations for system parameters or user preference data. data register detail (msb) (lsb) d7 d6 d5 d4 d3 d2 d1 d0 nv nv nv nv nv nv nv nv
x9250 fn8165 rev.3.00 page 5 of 20 august 29, 2006 figure 1. detailed potent iometer block diagram write in process the contents of the data registers are saved to nonvolatile memory when the cs pin goes from low to high after a complete write sequence is received by the device. the progress of this internal write operation can be monitored by a write in process bit (wip). the wip bit is read with a read status command. instructions identification (id) byte the first byte sent to the x9250 from the host, following a cs going high to low, is called the identification byte. the most significant four bits of the slave address are a device type identifier, for the x9250 this is fixed as 0101[b] (refer to figure 2). the two least significant bits in the id byte select one of four devices on the bus. the physical device address is defined by the state of the a 0 - a 1 input pins. the x9250 compares the serial data stream with the address input state; a successful compare of both address bits is required for the x9250 to successfully continue the command sequence. the a 0 - a 1 inputs can be actively driven by cmos input signals or tied to v cc or v ss . the remaining two bits in the slave byte must be set to 0. figure 2. identification byte format instruction byte the next byte sent to the x9250 contains the instruction and register pointer info rmation. the four most significant bits are the instruction. the next four bits point to one of the four pots and, when applicable, they point to one of four associated registers. the format is shown below in figure 3. figure 3. instruction byte format the four high order bits of th e instruction byte specify the operation. the next two bits (r 1 and r 0 ) select one of the four registers that is to be acted upon when a register oriented instruction is issued. the last two bits (p1 and p 0 ) selects which one of the four potentiometers is to be affected by the instruction. serial data path from interface circuitry register 0 register 1 register 2 register 3 serial bus input parallel input counter register inc/dec logic up/dn clk modified sck up/dn v h /r h v l /r l v w /r w 88 c o u n t e r d e c o d e if wcr = 00[h] then v w /r w = v l /r l if wcr = ff[h] then v w /r w = v h /r h wiper (one of four arrays) (wcr) bus 1 00 0 0 a1 a0 device type identifier device address 1 i1 i2 i3 i0 r1 r0 p1 p0 pot select register select instructions
x9250 fn8165 rev.3.00 page 6 of 20 august 29, 2006 four of the ten instructions are two bytes in length and end with the transmission of the instruction byte. these instructions are: ? xfr data register to wiper counter register ?this transfers the contents of on e specified data register to the associated wiper counter register. ? xfr wiper counter register to data register ?this transfers the contents of the specified wiper counter register to the specified associated data register. ? global xfr data register to wiper counter regiter ? this transfers the contents of all specified data regis- ters to the associated wiper counter registers. ? global xfr wiper counter register to data regiter ? this transfers the contents of all wiper counter regis- ters to the specified associated data registers. the basic sequence of the two byte instructions is illustrated in figure 4. th ese two-byte instructions exchange data between the wcr and one of the data registers. a transfer from a data register to a wcr is essentially a write to a stat ic ram, with the static ram controlling the wiper position. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to nonvolatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the four potentiometers and one of its associated registers; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. five instructions require a three-byte sequence to complete. these instructions transfer data between the host and the x9250; either between the host and one of the data registers or direct ly between the host and the wiper counter register. these instructions are: ? read wiper counter register ?read the current wiper position of the selected pot, ? write wiper counter register ?change current wiper position of the selected pot, ? read data register ?read the contents of the selected data register; ? write data register ?write a new value to the selected data register. ? read status ?this command returns the contents of the wip bit which indicates if the internal write cycle is in progress. the sequence of these operations is shown in figure 5 and figure 6. the final command is increment/decrement. it is different from the other comm ands, because it?s length is indeterminate. once the co mmand is issued, the master can clock the selected wiper up and/or down in one resistor segment steps; ther eby, providing a fine tuning capability to the host. fo r each sck clock pulse (t high ) while si is high, the se lected wiper will move one resistor segment towards the v h /r h terminal. similarly, for each sck clock pulse while si is low, the selected wiper will move one resistor segment towards the v l /r l terminal. a detailed illustra tion of the sequence and timing for this operation are shown in figure 7 and figure 8.
x9250 fn8165 rev.3.00 page 7 of 20 august 29, 2006 figure 4. two-byte instruction sequence figure 5. three-byte instruction sequence (write) figure 6. three-byte instruction sequence (read) figure 7. increment/decrement instruction sequence 010100a1a0 i3 i2 i1 i0 r1 r0 p1 p0 sck si cs 0 1 0 1 a1 a0 i3 i2 i1 i0 r1 r0 p1 p0 scl si d7 d6 d5 d4 d3 d2 d1 d0 cs 00 0 1 0 1 a1 a0 i3 i2 i1 i0 r1 r0 p1 p0 scl si cs 00 s0 d7 d6 d5 d4 d3 d2 d1 d0 dont care 010100a1a0 i3 i2 i1 i0 0 p1 p0 sck si i n c 1 i n c 2 i n c n d e c 1 d e c n 0 cs
x9250 fn8165 rev.3.00 page 8 of 20 august 29, 2006 figure 8. increment/decrement timing limits table 1. instruction set instruction instruction set operation i 3 i 2 i 1 i 0 r 1 r 0 p 1 p 0 read wiper counter register 10010 0p 1 p 0 read the contents of the wiper counter register pointed to by p 1 - p 0 write wiper counter register 10100 0p 1 p 0 write new value to the wiper counter register pointed to by p 1 - p 0 read data register 1 0 1 1 r 1 r 0 p 1 p 0 read the contents of the data register pointed to by p 1 - p 0 and r 1 - r 0 write data register 1 1 0 0 r 1 r 0 p 1 p 0 write new value to the data register pointed to by p 1 - p 0 and r 1 - r 0 xfr data register to wiper counter register 1101r 1 r 0 p 1 p 0 transfer the contents of the data register pointed to by r 1 - r 0 to the wiper counter register pointed to by p 1 - p 0 xfr wiper counter register to data register 1110r 1 r 0 p 1 p 0 transfer the contents of the wiper counter register pointed to by p 1 - p 0 to the register pointed to by r 1 - r 0 global xfr data register to wiper counter register 0001r 1 r 0 0 0 transfer the contents of the data registers pointed to by r 1 - r 0 of all four pots to their respective wiper counter register global xfr wiper counter register to data register 1000r 1 r 0 0 0 transfer the contents of all wiper counter registers to their respective data registers pointed to by r 1 - r 0 of all four pots increment/decrement wiper counter register 00100 0p 1 p 0 enable increment/decrement of the wiper counter register pointed to by p 1 - p 0 read status (wip bit) 0 1010 0 0 1r ead the status of the internal write cycle, by checking the wip bit. sck si v w /r w inc/dec cmd issued t wrid voltage out
x9250 fn8165 rev.3.00 page 9 of 20 august 29, 2006 instruction format notes: (1) ?a1 ~ a0?: stands for the device addresses sent by the master. (2) wpx refers to wiper position data in the counter register (2) ?i?: stands for the increment operation, si held high during active sck phase (high). (3) ?d?: stands for the decrement operation, si held low during active sck phase (high). read wiper count er register(wcr) write wiper counter register (wcr) read data register (dr) write data register (dr) transfer data register (dr) to wiper counter register (wcr) cs falling edge device type identifier device addresses instruction opcode wcr addresses wiper position (sent by x9250 on so) cs rising edge 010100 a 1 a 0 100100 p 1 p 0 w p 7 w p 6 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode wcr addresses data byte (sent by host on si) cs rising edge 010100 a 1 a 0 101000 p 1 p 0 w p 7 w p 6 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses data byte (sent by x9250 on so) cs rising edge 010100 a 1 a 0 1011 r 1 r 0 p 1 p 0 w p 7 w p 6 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses data byte (sent by host on si) cs rising edge high-voltage write cycle 010100 a 1 a 0 1100 r 1 r 0 p 1 p 0 w p 7 w p 6 w p 5 w p 4 w p 3 w p 2 w p 1 w p 0 cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses cs rising edge 010100 a 1 a 0 1101r1r0p1p0
x9250 fn8165 rev.3.00 page 10 of 20 august 29, 2006 transfer wiper counter register (wcr) to data register (dr) increment/decrement wipe r counter register (wcr) global transfer data register (dr) to wiper counter register (w cr) global transfer wiper counter reg ister (wcr) to da ta register ( dr) read status cs falling edge device type identifier device addresses instruction opcode dr and wcr addresses cs rising edge high-voltage write cycle 010100 a 1 a 0 1110 r 1 r 0 p 1 p 0 cs falling edge device type identifier device addresses instruction opcode wcr addresses increment/decrement (sent by master on si) cs rising edge 010100 a 1 a 0 0010xx p 1 p 0 i/d i/d . . . . i/d i/d cs falling edge device type identifier device addresses instruction opcode dr addresses cs rising edge 010100 a 1 a 0 0001 r 1 r 0 00 cs falling edge device type identifier device addresses instruction opcode dr addresses cs rising edge high-voltage write cycle 010100 a 1 a 0 1000 r 1 r 0 00 cs falling edge device type identifier device addresses instruction opcode data byte (sent by x9250 on so) cs rising edge 010100 a 1 a 0 010100010000000 w i p
x9250 fn8165 rev.3.00 page 11 of 20 august 29, 2006 absolute maximum ratings temperature under bias ........................ -65 to +135 ? c storage temperature ............................. -65 to +150 ? c voltage on sck, scl or any address input with respect to v ss ................................. -1v to +7v voltage on v+ (referenced to v ss )........................ 10v voltage on v- (referenced to v ss )........................-10v (v+) - (v-) .............................................................. 12v any v h /r h ..............................................................v+ any v l /r l .................................................................v- lead temperature (soldering, 10s) .................. +300 ? c i w (10s) ............................................................15ma comment stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any ot her conditions above those listed in the operational sections of this spec ification) is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. potentiometer characteristics (over recommended operating condit ions unless otherwise stated.) notes: (1) absolute linearity is utilized to determ ine actual wiper voltage versus expected vo ltage as determined by wiper position whe n used as a potentiometer. (2) relative linearity is utilized to deter mine the actual change in voltage between two successive tap posit ions when used as a potentiom- eter. it is a measure of the error in step size. (3) mi = rtot/255 or (v h /r h - v l /r l )/255, single pot (4) individual array resolutions. symbol parameter limits test conditions min. typ. max. unit end to end resistance tolerance 20 % power rating 50 mw +25c, each pot i w wiper current 7.5 ma r w wiper resistance 150 250 ? wiper current = ? 1ma vv+ voltage on v+ pin x9250 +4.5 +5.5 v x9250-2.7 +2.7 +5.5 vv- voltage on v- pin x9250 -5.5 -4.5 v x9250-2.7 -5.5 -2.7 v term voltage on any v h /r h or v l /r l pin v- v+ v noise -120 dbv ref: 1khz resolution (4) 0.6 % absolute linearity (1) 1 mi (3) v w(n)(actual) - v w(n)(expected) relative linearity (2) 0.6 mi (3) v w(n + 1 - [v w(n) + mi ] temperature coefficient of r total ? 300 ppm/c ratiometric temperature coefficient 20 ppm/c c h /c l /c w potentiometer capacitances 10/10/25 pf see circuit #3 recommended operating conditions temp min. max. commercial 0 ? c+70 ? c industrial -40 ? c+85 ? c device supply voltage (v cc ) limits (4) x9250 5v ? 10% x9250-2.7 2.7v to 5.5v
x9250 fn8165 rev.3.00 page 12 of 20 august 29, 2006 d.c. operating characteristics (over the recommended operating cond itions unless otherwise specified.) endurance and data retention capacitance power-up timing power up and down requirement the are no restrictions on the sequencing of the bias supplies v cc , v+, and v- provided that all three supplies reach their final values within 1msec of each other. at all times, the voltages on the potentiometer pins must be less than v+ and more than v-. the recall of the wiper position from nonvol atile memory is not in effect until all supplies reach their final value. the v cc ramp rate spec is always in effect. notes: (5) this parameter is periodically sampled and not 100% tested (6) t pur and t puw are the delays required from the time the third (last) power supply (v cc , v+ or v-) is stable until the specific instruction can be issued. these parameters are periodically sampled and not 100% tested. (7) sample tested only. a.c. test conditions symbol parameter limits test conditions min. typ. max. unit i cc1 v cc supply current (active) 400 a f sck = 2mhz, so = open, other inputs = v ss i cc2 v cc supply current (nonvolatile write) 1maf sck = 2mhz, so = open, other inputs = v ss i sb v cc current (standby) 5 a sck = si = v ss , addr. = v ss i li input leakage current 10 a v in = v ss to v cc i lo output leakage current 10 a v out = v ss to v cc v ih input high voltage v cc x 0.7 v cc + 0.1 v v il input low voltage -0.5 v cc x 0.3 v v ol output low voltage 0.4 v i ol = 3ma parameter min. unit minimum endurance 100,000 data changes per bit per register data retention 100 years symbol test max. unit test conditions c out (5) output capacitance (so) 8 pf v out = 0v c in (5) input capacitance (a0, a1, si, and sck, cs) 6 pf v in = 0v symbol parameter min. max. unit t pur (6) power-up to initiation of read operation 1 ms t puw (6) power-up to initiation of write operation 5 ms t r v cc (7) v cc power up ramp rate 0.2 50 v/msec i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5
x9250 fn8165 rev.3.00 page 13 of 20 august 29, 2006 circuit #3 spice macro model e quivalent a.c. load circuit ac timing 10pf r h r total c h 25pf c w c l 10pf r w r l 5v 1533 ? 100pf sda output 2.7v 100pf 6\pero 3dudphwhu 0lq 0d[ 8qlw f sck ssi/spi clock frequency 2.0 mhz t cyc ssi/spi clock cycle time 500 ns t wh ssi/spi clock high time 200 ns t wl ssi/spi clock low time 200 ns t lead lead time 250 ns t lag lag time 250 ns t su si, sck, hold and cs input setup time 50 ns t h si, sck, hold and cs input hold time 75 ns t ri si, sck, hold and cs input rise time 2 s t fi si, sck, hold and cs input fall time 2 s t dis so output disable time 0 500 ns t v so output valid time 100 ns t ho so output hold time 0 ns t ro so output rise time 50 ns t fo so output fall time 50 ns t hold hold time 400 ns t hsu hold setup time 100 ns t hh hold hold time 100 ns t hz hold low to output in high z 100 ns t lz hold high to output in low z 100 ns t i noise suppression time constant at si, sck, hold and cs inputs tbd ns t cs cs deselect time 2 s t wpasu wp , a0 and a1 setup time 0 ns t wpah wp , a0 and a1 hold time 0 ns
x9250 fn8165 rev.3.00 page 14 of 20 august 29, 2006 high-voltage write cycle timing xdcp timing symbol table timing diagrams input timing symbol parameter typ. max. unit t wr high-voltage write cycle time (store instructions) 5 10 ms symbol parameter min. max. unit t wrpo wiper response time after the third (last) power supply is stable 10 s t wrl wiper response time after instruction issued (all load instructions) 10 s t wrid wiper response time from an active scl/sck edge (increment/decrement instruc- tion) 40 s waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance ... cs sck si so msb lsb high impedance t lead t h t su t fi t cs t lag t cyc t wl ... t ri t wh
x9250 fn8165 rev.3.00 page 15 of 20 august 29, 2006 output timing hold timing xdcp timing (for all load instructions) ... cs sck so si addr msb lsb t dis t ho t v ... ... cs sck so si hold t hsu t hh t lz t hz t hold t ro t fo cs sck si msb lsb vwx t wrl ... so high impedance
x9250 fn8165 rev.3.00 page 16 of 20 august 29, 2006 xdcp timing (for incremen t/decrement instruction) write protect and device address pins timing ... cs sck so si addr t wrid high impedance vwx ... inc/dec inc/dec ... cs wp a0 a1 t wpasu t wpah (any instruction)
x9250 fn8165 rev.3.00 page 17 of 20 august 29, 2006 applications information basic configurations of electronic potentiometers application circuits v r v w /r w +v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current 1rqlqyhuwlqj$psolilhu 9rowdjh5hjxodwru 2iivhw9rowdjh$gmxvwphqw &rpsdudwruzlwk+\vwhulvlv + ? v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + ? v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 ) v o (max) v ll = {r 1 /(r 1 +r 2 ) v o (min) 100k ? 10k ? 10k ? 10k ? -12v +12v tl072 + ? v s v o r 2 r 1 } }
x9250 fn8165 rev.3.00 page 18 of 20 august 29, 2006 application circuits (continued) attenuator filter inverting amplifier equivalent l-r circuit + ? v s v o r 3 r 1 v o = g v s -1/2 ? g ?? +1/2 g o = 1 + r 2 /r 1 fc = 1/(2 ? rc) + ? v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + ? v s r 2 r 4 r 1 = r 2 = r 3 = r 4 = 10k ? + ? v s r 2 r 1 r c } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + ? r 2 + ? r 1 } } r a r b frequency ? r 1 , r 2 , c amplitude ? r a , r b c v o
x9250 fn8165 rev.3.00 page 19 of 20 august 29, 2006 thin shrink small outline package family (tssop) n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail x end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane mdp0044 thin shrink small outline package family symbol 14 ld 16 ld 20 ld 24 ld 28 ld tolerance a 1.20 1.20 1.20 1.20 1.20 max a1 0.10 0.10 0.10 0.10 0.10 0.05 a2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 5.00 6.50 7.80 9.70 0.10 e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference rev. e 12/02 notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension ?e1? does not include interlead flash or protrusions. interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. dimensions ?d? and ?e1? are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994.
fn8165 rev.3.00 page 20 of 20 august 29, 2006 x9250 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2005-2006. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. small outline plast ic packages (soic) notes: 1. symbols are defined in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension d does not include mold flash, protrusions or gat e burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension e does not include interlead flash or protrusions . inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal for soldering to a substrate. 7. n is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width b, as measured 0.36mm (0.014 inch) or greate r above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millime ter. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m ? m24.3 (jedec ms-013-ad issue c) 24 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.020 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.5985 0.6141 15.20 15.60 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n24 247 ? 0 8 0 8 - rev. 1 4/06

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